of 2

Abstract (1) | Field Effect Transistor | Mosfet

All materials on our website are shared by users. If you have any questions about copyright issues, please report us to resolve them. We are always happy to assist you.
Study and Analysis of Nanoscale Novel Semiconductor Devices for VLSI Circuits Design   Abstract:     The metal–oxide–semiconductor field-effect transistor (MOSFET, MOSFET, or MOS FET) is a transistor used for amplifying or switching electronic signals. Although the MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B) terminals, the body (or substrate) of the MOSFET often is connected to the source terminal, making it a three-terminal device like other field
  Study and Analysis of Nanoscale Novel Semiconductor Devices for VLSI Circuits Design     Abstract: The metal–oxide–semiconductor field-effect transistor ( MOSFET , MOS-FET , or MOS FET ) is a transistor used for amplifying or switchingelectronic signals. Although the MOSFET is a four-terminal device with source(S), gate (G), drain (D), and body (B) terminals, the body (or substrate) of theMOSFET often is connected to the source terminal, making it a three-terminaldevice like other field-effect transistors. Because these two terminals arenormally connected to each other (short-circuited) internally, only threeterminals appear in electrical diagrams. The dual-gate MOSFET has a tetrode configuration, where both gates controlthe current in the device. It is commonly used for small-signal devices in radiofrequency applications where biasing the drain-side gate at constant potentialreduces the gain loss caused by Miller effect, replacing two separatetransistors in cascode configuration. Other common uses in RF circuitsinclude gain control and mixing (frequency conversion). The FinFET , is a double-gate silicon-on-insulator device, one of a number ofgeometries being introduced to mitigate the effects of short channels andreduce drain-induced barrier lowering. The fin refers to the narrow channelbetween source and drain. A thin insulating oxide layer on either side of the finseparates it from the gate. SOI FinFETs with a thick oxide on top of the fin arecalled double-gate  and those with a thin oxide on top as well as on the sidesare called triple-gate  FinFETs. The Single Electron Transistor is a new type of switching device that usescontrolled electron tunneling to amplify current. It consists of two electrodesknown as the drain  and the source  , connected through tunnel junctions to onecommon electrode with a low self-capacitance, known as the island  . Theelectrical potential of the island can be tuned by a third electrode, known asthe gate  , capacitively coupled to the island. Tunnel Field-Effect Transistor (FET) is a gated-diode operating based onband-to-band tunneling at the junction. Key device parameters are thebandgap of the source material, the gate-to-channel coupling, the gatedielectric thickness and permittivity and the junction profile includingabruptness and doping level. Gate-All-Around FETs are similar in concept to FinFETs except that the gatematerial surrounds the channel region on all sides. Depending on design,gate-all-around FETs can have two or four effective gates. Gate-all-aroundFETs have been successfully built around a silicon nanowire andetched InGaAs nanowires.  A carbon nanotube field-effect transistor (CNTFET) refers to a field-effecttransistor that utilizes a single carbon nanotube or an array of carbonnanotubes as the channel material instead of bulk silicon in thetraditional MOSFET structure. Carbon nanotubes are cylindrical sheets of oneore more concentric layers of carbon atoms. Single-wall carbon nanotubesshow superior electrical properties and are considered promising candidatesfor future Nano electronic applications, either as interconnects or activedevices.By analyzing the parameters & equations pertaining to the basic MOSFET, wecan study the equations for Drain Current (I D ), Gate-Source Voltage (V GS ),Drain-Source Voltage (V DS ), Threshold Voltage (V TH ), Trans conductance (g m ),Output Resistance (R out ), Channel Length(L), Width (W). We can also plot theI D vs V DS graph at different values of V GS  By studying the equations obtained for the above design parameters we aimto improve the efficiency of the above FET ʼ s by1)   Reducing the length of the channel, which implies smaller area.2)   Reducing the leakage current, which in turn reduces the powerdissipation.3)   Increasing the drain current to improve the switching which in turnenhances the speed.4)   Reducing the delay of the circuit.Project Mentor: Eric Savio Sales De Andrade (09104079)Dr. Balwinder Raj Vivek Kumar Singh (09104097)Assistant ProfessorDepartment of Electronics & CommunicationNIT Jalandhar
Related Search
We Need Your Support
Thank you for visiting our website and your interest in our free products and services. We are nonprofit website to share and download documents. To the running of this website, we need your help to support us.

Thanks to everyone for your continued support.

No, Thanks